Run Pi in SPI slave mode and supply external SPI clock source which will also be used as audio clock rate. It will still act as it's own SPI master but with the external clock.
USE DAC in TDM mode with 8 channels on one I2S pin
Demultiplexing SPI
multiplexer 16bit pr. channel to 2 bit per channel (ie. 2 channels per 32 bit sample) and write 20 channels in total this way where the 16 is the actual output and the last 4 are unused (but can be used for sync)
http://www.dimdim.gr/2014/12/the-rasberry-pi-audio-out-through-i2s/
Midi Input: http://www.samplerbox.org/article/midiinwithrpi
Todo:
Bring logic analyzer and rpi3 and probes
Each sample uses 1 bit as sync bit. Channel 0 has the bit set to 1, the rest has it set to 0. If the FPGA detects a drift, (pattern doesn't match) it can shift the input one bit and test again - repeating until the pattern matches again. While seeking for a new lock pattern, the output should be muted. When the lock pattern has been found again a number of samples should be processed before the output is unmuted again in order to make sure that we didn't simply find an audio pattern that matched the lock pattern (highly unlikely!)
CS on the SPI can be used as a reset mechanism, ie. CS high will reset the FPGA channel counter. CS could be set high for each 1024 samples or similar, key-frame style.
root@raspberrypi3:/var/volatile/tmp# spidev_test -D /dev/spidev0.0 -i /tmp/stuff -s 64000000 spi mode: 0x0 bits per word: 8 max speed: 64000000 Hz (64000 KHz) Mem: 164996K used, 782672K free, 131260K shrd, 2752K buff, 138176K cached CPU: 0% usr 30% sys 0% nic 68% idle 0% io 0% irq 0% sirq Load average: 0.88 0.72 0.36 4/97 437 PID PPID USER STAT VSZ %VSZ %CPU COMMAND 437 327 root R 257m 28% 23% spidev_test -D /dev/spidev0.0 -i /tmp/ 153 2 root RW 0 0% 8% [spi0] 422 307 root R 2980 0% 0% top -d1
Serie modstand på transfer lines på ~100ohm for at undgå relfektions effekter.
Set static ip address in /etc/networking/interfaces
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