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--- dev:dg_in_a_box:diary [2017/12/12 21:20] – [2017-12-12] deva
+++ dev:dg_in_a_box:diary [2018/04/17 21:07] – suhr
@@ Line 1: / Line 1: @@
 ======Diary======
+Future:
+  * http://www.ti.com/lit/ml/mpqf071b/mpqf071b.pdf
+  * https://www.toradex.com/community/questions/5125/spi-kernel-driver.html
+  * http://linux-sunxi.org/SPIdev
+  * BCM SPI driver for userspace SPI (faster than spidev): [[https://www.raspberrypi.org/forums/viewtopic.php?f=41&t=50230&p=400975&hilit=spi%2bspeed#p400975|link]]
+  * Raspberry Pi SPI speed table: [[https://elinux.org/index.php?title=RPi_SPI#Speed_2|link]]
+  * https://github.com/imr/ngspice
+  * Kicad with Spice integration: [[https://archive.fosdem.org/2017/schedule/event/spice_kicad/|link]]
+=====2018-04-17=====
+We made initial schematic in kicad.
+Next define electric bla bla in pcm3168A component. Make sure that every pins are connected to something (mark unused as unused). Continue until electrical rule check is passed.
+=====2018-02-27=====
+We (re)started working with kicad to define the PCM and FPGA chips.
+Information about the component library file format:
+http://kicad-pcb.org/help/file-formats/
+We are considering using the iCE40 Ultra (iCE5LP4K) instead of the iCE40HX8K.
+=====2018-01-23=====
+Somewthing about blocking and non-blocking assignment in verilog:
+  * https://class.ee.washington.edu/371/peckol/doc/Always@.pdf
+Today we decided that Verilog sucks and added vhd2vl to toolchain.
+Next time we will implement shiftregister in vhdl.
+=====2018-01-16=====
+Today we got two FPGAs working together as a serial coupled shift register. (The working code has been committed to git.)
+Next time we will double the clock rate output from the first to the second.
+{{:dev:dg_in_a_box:sketch.jpg?400|}}
+=====2017-12-26=====
+Today we got it working. Now we have a working shiftregister.
+We tried to serial couple another fpga, but couldn't make the clock output work as expected.
+Next we want to use the second fpga to emulate the CODECs and the channel reset mechanism. Maybe also try to make the shift register as a module so we can 'stack' them.
+=====2017-12-19=====
+Today we had the fpga tool-chain working. Next time Jonas will bring his PSU...
+We experimented with a shift register implementation. Didn't get it working though...
+Next time we will make it work! **Analyse clock and MOSI signals with scope.** As a home assignment, read up on Verilog timing.
 =====2017-12-12=====

dev/dg_in_a_box/diary.txt · Last modified: 2018/04/17 21:08 by suhr

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