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dev:dg_in_a_box:diary [2018/01/11 13:18] – [Diary] deva | dev:dg_in_a_box:diary [2018/04/03 20:57] – suhr | ||
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Future: | Future: | ||
+ | * http:// | ||
* https:// | * https:// | ||
* http:// | * http:// | ||
+ | * BCM SPI driver for userspace SPI (faster than spidev): [[https:// | ||
+ | * Raspberry Pi SPI speed table: [[https:// | ||
+ | * https:// | ||
+ | * Kicad with Spice integration: | ||
+ | |||
+ | =====2018-02-27===== | ||
+ | We (re)started working with kicad to define the PCM and FPGA chips. | ||
+ | |||
+ | Information about the component library file format: | ||
+ | http:// | ||
+ | |||
+ | We are considering using the iCE40 Ultra (iCE5LP4K) instead of the iCE40HX8K. | ||
+ | =====2018-01-23===== | ||
+ | Somewthing about blocking and non-blocking assignment in verilog: | ||
+ | |||
+ | * https:// | ||
+ | |||
+ | Today we decided that Verilog sucks and added vhd2vl to toolchain. | ||
+ | |||
+ | Next time we will implement shiftregister in vhdl. | ||
+ | =====2018-01-16===== | ||
+ | Today we got two FPGAs working together as a serial coupled shift register. (The working code has been committed to git.) | ||
+ | |||
+ | Next time we will double the clock rate output from the first to the second. | ||
+ | |||
+ | {{: | ||
=====2017-12-26===== | =====2017-12-26===== | ||
Today we got it working. Now we have a working shiftregister. | Today we got it working. Now we have a working shiftregister. |